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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
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Advance Product Specification
Features
* * * Operating Temperature Range: -55 C to +125 C Low-power advanced CMOS FLASH process memory cells immune to static single event upset In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs * * * Endurance of 20,000 program/erase cycles IEEE Std 1149.1 boundary-scan (JTAG) support Cascadable for storing longer or multiple bitstreams Dual configuration modes * * * * * Serial Slow/Fast configuration (up to 20 MHz) Parallel (up to 160 Mbps at 20 MHz)
Description
Xilinx introduces the QProTM XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM (see Figure 1). The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that require operation over the full military temperature range. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. See Figure 3. Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration PROMs.
CLK CE OE/Reset
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals 3.3V or 2.5V output capability Available in plastic VQ44 packaging only Design support using the Xilinx Alliance SeriesTM and Xilinx Foundation SeriesTM software packages JTAG command initiation of standard FPGA configuration
TCK TMS TDI TDO
Control and JTAG Interface
Data Memory Address Data Serial or Parallel Interface
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CEO D0 DATA (Serial or Parallel [Express/SelectMAP] Mode) D[1:7] Express Mode and SelectMAP Interface
CF
DS026_01_021000
Figure 1: XQ18V04 Series Block Diagram
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
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Xilinx FPGAs and Compatible PROMs
Table 1: FPGA Configuration Storage Requirements Device XQV300 XQV600 XQV1000 XQ2V1000 XQ2V3000 XQ2V6000 Configuration Bits 1,751,808 3,607,968 6,127,744 3,752,736 9,594,656 19,759,904 XQ18V04 PROMs 1 1 2 1 3 5 *
left unconnected when the PROM operates in serial mode. Express/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements.
Initiating FPGA Configuration
The XQ18V04 device incorporates a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses CF Low for 300 to 500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. The Xilinx iMPACTTM software can also issue a JTAG CONFIG command to initiate FPGA configuration through the "Load FPGA" setting.
Capacity
Table 2: PROM Storage Capacity Device XQ18V04 Configuration Bits 4,194,304
Selecting Configuration Modes
The XQ18V04 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XQ18V04 device. This control register is accessible through JTAG, and is set using the "Parallel mode" setting on the Xilinx iMPACT software. Serial output is the default programming mode.
Connecting Configuration PROMs
When connecting the FPGA device with the configuration PROM (see Figure 3): * * The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) in Master Serial and Master SelectMAP modes. The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection ensures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of the first FPGA device, provided that DONE is not permanently grounded. CE also can be tied permanently Low, but this keeps the DATA output active and causes an unnecessary supply current of 20 mA maximum. D1-D7 remain in a high-impedance state and can be
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (see Figure 2). Multiple XQ18V04 devices can be cascaded by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all the XQ18V04 devices in the chain are interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 3. After configuration is complete, the address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low.
* *
*
*
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
Vcc
Vcco
Vcc
Vcco
Vcc 4.7K Vcc DIN MODE PINS* DOUT Vcc DIN MODE PINS*
Vcc Vcco
D0
Vcc Vcco
D0
Xilinx FPGA
Vcc
Xilinx FPGA Slave Serial
XQ18V04 Cascaded PROM
1 2 3 4 TDI TMS TCK CLK CE CEO OE/RESET CF GND TDO GND TDI TMS TCK
XQ18V04 First PROM
CLK CE CEO OE/RESET CF TDO
Master Serial
J1
TDI TMS TCK TDO
**
CCLK DONE INIT PROGRAM TDI TMS TCK TDO CCLK DONE INIT PROGRAM TDI TMS TCK TDO
* For Mode pin connections, refer to the appropriate FPGA data sheet. ** Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others.
DS026_08_120103
Figure 2: JTAG Chain for Configuring Devices in Master Serial Mode
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DOUT
OPTIONAL Daisy-chained FPGAs with different configurations VCC 4.7K VCC OPTIONAL Slave FPGAs with identical configurations Vcco Vcc
FPGA
Modes*
**
VCC VCCO DATA First CLK PROM CEO CE OE/RESET CF
DIN CCLK DONE INIT PROGRAM (Low Resets the Address Pointer)
DATA CLK CE OE/RESET CF Cascaded PROM
*For Mode pin connections, refer to the appropriate FPGA data sheet. **Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others.
Master Serial Mode
I/O* I/O* Modes*** CS WRITE 1K 1K VCC External Osc 3.3V 4.7K XQ18V04 CLK 8 D[0:7] CE OE/RESET CEO CF VCC VCCO VCC VCCO
Virtex Select MAP NC BUSY CCLK PROGRAM D[0:7] DONE INIT
**
*CS and WRITE must be pulled down to be used as I/O. One option is shown. **Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others. ***For Mode pin connections, refer to the appropriate FPGA data sheet.
Virtex Select MAP Mode
To Additional Optional Daisy-chained Devices
VCC VCC 4.7K VCC VCCO D[0:7] CEO XQ18V04 CE CF PROGRAM DONE INIT CCLK 8 4.7K VCC VCCO VCC M0 CS1 M1 DOUT M0 CS1 M1
XQ4000XL
DOUT Optional Daisy-chained XQ4000XL
D[0:7] D[0:7] PROGRAM DONE INIT CCLK To Additional Optional Daisy-chained Devices
OE/RESET CLK
External Osc
XQ4000XL Express Mode
DS082_05_120103
Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode (c) XQ4000XL Express Mode (dotted lines indicate optional connection)
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DS125 (v1.0) December 16, 2003 Advance Product Specification
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM state regardless of the state of the OE input. JTAG pins TMS, TDI, and TDO can be in a high-impedance state or High. See Table 3.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) may have power applied in any order. This makes the PROM devices immune to power supply sequencing issues.
Customer Control Bits
The XQ18V04 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using "Skip User Array" in Xilinx iMPACT software. The iMPACT software can set these bits to enable the optional JTAG read security, parallel configuration mode, or CF-->D4 pin function.
Reset Activation
On power up, OE/RESET is held Low until the XQ18V04 is active (1 ms) and is able to supply data after receiving a CCLK pulse from the FPGA. OE/RESET is connected to an external resistor to pull OE/RESET High releasing the FPGA INIT and allowing configuration to begin. OE/RESET is held Low until the XQ18V04 voltage reaches the operating voltage range. If the power drops below 2.0V, the PROM will reset. OE/RESET polarity is NOT programmable. See Figure 4 for power-on requirements.
3.6V Recommended Operating Range 3.0V Recommended
Volts
VCCINT Rise Time
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance Table 3: Truth Table for PROM Control Inputs Control Inputs OE/RESET High Low High Low CE Low Low High High Internal Address
0V 0ms 1ms Time (ms)
50ms
ds026_10_102303
Figure 4: VCCINT Power-On Requirements
Outputs DATA Active High-Z High-Z High-Z High-Z CEO High Low High High High ICC Active Reduced Active Standby Standby
If address < TC(1): increment If address > TC(1): don't change Held reset Held reset Held reset
Notes: 1. TC = Terminal Count = highest address value. TC + 1 = address 0.
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In-System Programming
In-System Programmable PROMs can be programmed individually, or two or more can be chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 5. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx iMPACT software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-impedance state or held at clamp levels during in-system programming.
boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a guaranteed endurance level of 2,000 in-system program/erase cycles and a minimum data retention of ten years. Each device meets all functional, performance, and data retention specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 4 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 4: Data Security Options Default = Reset Read Allowed Program/Erase Allowed Verify Allowed Set Read Inhibited via JTAG Program/Erase Allowed Verify Inhibited
OE/RESET
The ISP programming algorithm requires issuance of a reset that will cause OE to go Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130, the Xilinx MultiPRO, or a third party device programmer. This provides the added flexibility of using pre-programmed devices in board design and
V CC
GND
(a)
(b)
DS026_02_011100
Figure 5: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 6. The ISP Status field, IR[4], contains logic "1" if the device is currently in ISP mode; otherwise, it will contain logic "0". The Security field, IR[3], will contain logic "1" if the device has been programmed with the security option turned on; otherwise, it will contain logic "0".
IR[7:5] TDI-> Notes: 000 IR[4] ISP Status IR[3] Security IR[2] 0 IR[1:0] 01 ->TDO
IEEE 1149.1 Boundary Scan (JTAG)
The XQ18V04 is fully compliant with the IEEE Std. 1149.1 Boundary Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary-scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XQ18V04 device. Table 5 lists the required and optional boundary-scan instructions supported in the XQ18V04. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. Table 5: Boundary Scan Instructions Boundary-Scan Command BYPASS SAMPLE/ PRELOAD Binary Code [7:0] 11111111 00000001 Description Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD operation Enables boundary-scan EXTEST operation Enables boundary-scan CLAMP operation All outputs in high-impedance state simultaneously Enables shifting out 32-bit IDCODE Enables shifting out 32-bit USERCODE Initiates FPGA configuration by pulsing CF pin Low
1. IR[1:0] = 01 is specified by IEEE Std. 1149.1. Figure 6: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence
Boundary-Scan Register
The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the XQ18V04 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin.
Required Instructions
EXTEST
00000000
Optional Instructions
CLAMP
11111010
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (50h for the XQ18V04) a = the ISP PROM product ID (26h for the XQ18V04) c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1.
HIGHZ
11111100
IDCODE USERCODE
11111110 11111101
XQ18V04 Specific Instructions
CONFIG
11101110
Instruction Register
The Instruction Register (IR) for the XQ18V04 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Table 6 lists the IDCODE register values for the XQ18V00 devices. Table 6: IDCODEs Assigned to XQ18V04 Devices ISP PROM XQ18V04 IDCODE 05036093h
R
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XQ18V04 device. If the device is blank or was not loaded during programming, the USERCODE register will contain FFFFFFFFh.
XQ18V04 TAP Characteristics
The XQ18V04 device performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XQ18V04 TAP are described as follows.
TCKMIN
TAP Timing
Figure 7 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations.
TCK
TMSS TMSH
TMS
TDIS TDIH
TDI
TDOV
TDO
DS026_04_020300
Figure 7: Test Access Port Timing
TAP AC Parameters
Table 7 shows the timing parameters for the TAP waveforms shown in Figure 7. Table 7: Test Access Port Timing Parameters Symbol TCKMIN TMSS TMSH TDIS TDIH TDOV Parameter TCK minimum clock period TMS setup time TMS hold time TDI setup time TDI hold time TDO valid delay Min 200 10 25 10 25 Max 25 Units ns ns ns ns ns ns
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
Absolute Maximum Ratings(1,2)
Table 8: Absolute Maximum Ratings Symbol VCCINT/VCCO VIN VTS TSTG TJ Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to High-Z output Storage temperature (ambient) Junction temperature Ceramic Plastic TSOL Maximum soldering temperature Value -0.5 to +4.0 -0.5 to +5.5 -0.5 to +5.5 -65 to +150 +150 +125 +220 Units V V V C C C C
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +7.0V, provided this overshoot or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Table 9: Recommended Operating Conditions Symbol VCCINT Parameter Internal voltage supply (TC = -55 C to +125 C) Internal voltage supply (TJ = -55 C to +125 C) VCCO Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation VIL VIH VO TVCC Low-level input voltage High-level input voltage Output voltage VCCINT rise time from 0V to nominal voltage1 Ceramic Plastic Min 3.0 3.0 3.0 2.3 0 2.0 0 1 Max 3.6 3.6 3.6 2.7 0.8 5.5 VCCO 50 Units V V V V V V V ms
Notes: 1. At power up, the device requires the VCCINT power supply to monotonically rise from 0V to nominal voltage within the specified VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly.
Quality and Reliability Characteristics
Table 10: Reliability Characteristics Symbol TDR NPE VESD Data retention Program/erase cycles (Endurance) Electrostatic discharge (ESD) Description Min 10 20,000 2,000 Max Units Years Cycles Volts
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DC Characteristics Over Operating Conditions
Table 11: DC Characteristics Symbol VOH Parameter High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs VOL Low-level output voltage for 3.3V outputs Low-level output voltage for 2.5V outputs ICC ICCS IILJ IIL IIH CIN and COUT Supply current, active mode Supply current, standby mode JTAG pins TMS, TDI, and TDO Input leakage current Input and output High-Z leakage current Input and output capacitance VCC = MAX VIN = GND VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz Test Conditions IOH = -4 mA IOH = -500 A IOL = 8 mA IOL = 500 A 25 MHz Min 2.4 90% VCCO -100 -10 -10 Max 0.4 0.4 50 20 10 10 10 Units V V V V mA mA A A A pF
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM
.AC
Characteristics Over Operating Conditions for XQ18V04
CE
TSCE THCE
OE/RESET
TLC THC TCYC THOE
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
DS026_06_012000
Figure 8: Pin-to-Pin Timing Diagram
Table 12: AC Timing Characteristics for Single Device Symbol TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE OE/RESET to data delay CE to data delay CLK to data delay Data hold from CE, OE/RESET, or CLK CE or OE/RESET to data float delay(2) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (to guarantee proper counting)(3) CE High time (to guarantee proper counting) OE/RESET hold time (guarantees counters are reset) Description Min 0 50 10 10 25 2 25 Max 10 20 20 25 Units ns ns ns ns ns ns ns ns ms s ns
Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 s, TCE = 2 s.
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AC Characteristics Over Operating Conditions When Cascading for XQ18V04
OE/RESET
CE
CLK
TCDF TOCE First Bit TOOE
DATA
Last Bit TOCK
CEO
DS026_07_020300
Figure 9: Pin-to-Pin Timing Diagram for Cascaded Devices Table 13: AC Timing Characteristics for Cascaded Devices Symbol TCDF TOCK TOCE TOOE Description CLK to data float delay(2,3) CLK to CEO delay(3) CE to CEO delay(3) OE/RESET to CEO delay(3) Min Max 25 20 20 20 Units ns ns ns ns
Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
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Pinout and Pin Description
Table 14: Pin Names and Descriptions (pins not listed are "no connect") Pin Number Pin Name D0 Boundary Scan Order 4 3 D1 6 5 D2 2 1 D3 8 7 D4 24 23 D5 10 9 D6 17 16 D7 14 13 CLK OE/ RESET 0 20 19 18 CE 15 44-pin Function DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA IN DATA IN DATA OUT OUTPUT ENABLE DATA IN Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. When CE is High, this pin puts the device into standby mode and resets the address counter. The DATA output pin is in a high-impedance state, and the device is in low-power standby mode. 43 13 19 14 25 9 27 Pin Description D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. VQFP 40
D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Express/SelectMap mode. D1-D7 remain in HIGHZ state and can be left unconnected when the PROM operates in serial mode.
29
42
15
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QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Table 14: Pin Names and Descriptions (pins not listed are "no connect") (Continued) Pin Number Pin Name CF Boundary Scan Order 22 21 44-pin Function DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE Pin Description Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when OE/RESET goes Low or CE goes High. GND TMS TEST MODE SELECT GND is the ground connection. The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50 Kohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50 Kohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50 Kohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. Positive 3.3V supply voltage for internal logic and input buffers. Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers. 6, 18, 28, 41 5 VQFP 10
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CEO
13 14
21
TCK
TEST CLOCK
7
TDI
TEST DATA IN
3
TDO
TEST DATA OUT
31
VCCINT VCCO
17, 35, 38 8, 16, 26, 36
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Package Pin Diagrams PROM Package Pinout Compatibility
NC CLK D2 GND D0 NC VCCINT* NC VCCO VCCINT* NC
Table 15: PROM-to-PROM Pinout Compatibility for the VQFP44 Package VQ44 5 7
33 32 31 30 29 28 27 26 25 24 23 NC NC TDO NC D1 GND D3 VCCO D5 NC NC
1.
XQ18V04 TMS TCK TDI TDO CF N/C N/C VCCINT VCCO1
XQ17V16 N/C N/C N/C N/C N/C BUSY GND VPP VCC
NC NC TDI NC TMS GND TCK VCCO D4 CF NC
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34
3 31 10 24 37 35 8, 16, 26, 36
VQ44 Top View
12 13 14 15 16 17 18 19 20 21 22
The XQ18V04 supports 2.5-3.3V VCCO operation. The XQ17V16 only supports 3.3V.
NC OE/RESET D6 CE VCCO VCCINT* GND D7 NC CEO NC
*See pin descriptions.
DS082_13_102303
Figure 10: Package Pinout for the XQ18V04VQ44
Ordering Information
XQ18V04 VQ44 N
Device Number Package Type Manufacturing Grade
Device Ordering Options
Device Type XQ18V04 VQ44 Package 44-pin Plastic Thin Quad Flat Package Grade
N
Military Plastic
TJ = -55 C to +125 C
Revision History
The following table shows the revision history for this document. Date 12/16/03 Version 1.0 Revision First publication of this early access specification.
DS125 (v1.0) December 16, 2003 Advance Product Specification
www.xilinx.com 1-800-255-7778
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